The present invention relates to a semiconductor nonvolatile memory apparatus comprising transistors of which a threshold voltage can be electrically rewritten, or in particular to a semiconductor nonvolatile memory apparatus suitably used for electrically rewriting the threshold voltage frequently and a computer system using such an apparatus, or more in particular to a technical field in which a stable read operation of the semiconductor nonvolatile memory apparatus driven by a single source voltage is possible and the size of a semiconductor nonvolatile memory apparatus driven by a single source voltage can be reduced.
A semiconductor nonvolatile memory apparatus of a single-transistor-per-cell configuration which can collectively erase the stored information electrically is a flash memory. The flash memory has such a configuration that the area occupied for each bit is small and high integration is possible. For this reason, this memory has been closely watched recently and various research and development efforts are made actively on the structure and the method of driving it.
A first example that has thus far been suggested is a DINOR type described in xe2x80x9cSymposium on VLSI Circuits Digest of Technical Papersxe2x80x9d, pp.97-98, 1993; a second example is a NOR type described in the same papers, pp.99-100, 1993; a third example is an AND type described in the same papers, pp.61-62, 1994; and a fourth example is a HICR type described in xe2x80x9cInternational Electron Devices Meeting Tech. Dig.xe2x80x9d, pp.19-22.
With each of the above-mentioned types, at the time of the read operation, the word line potential is set to a source voltage Vcc and a low voltage of about 1 V is applied as a bit line potential to prevent weak electrons from being drawn, while information is read from memory cells by a sense amplifier circuit. Let the state in which electrons are stored in a floating gate be defined as an erase mode. In erase mode, the threshold voltage of the memory cell increases. Even if a word line is selected at the time of read operation, therefore, no drain current flows and the bit line potential is held at a precharge potential of 1 V. Let the state in which no electrons are injected (electrons are discharged) be defined as a write mode, on the other hand. In write mode, the threshold voltage value of the memory cell drops. When a word line is selected, therefore, a current begins to flow, and the bit line potential decreases below the precharge potential 1 V. The bit line potential is amplified by a sense amplifier thereby to judge a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d state of the information.
A first example so far suggested is an AND type described in xe2x80x9cInternational Electron Devices Meeting Tech. Dig.xe2x80x9d pp.991-993, 1992, and a second example is a HICR type described in the same papers, pp.19-22, 1993.
In each of these types, the operation of increasing the threshold voltage of a memory cell in the sector representing a unit of each word line is defined as an erase operation.
In the AND type described in xe2x80x9cSymposium on VLSI Circuits Digest of Technical Papersxe2x80x9d, pp.61-62, 1994, a high positive voltage of 16 V is applied to a selected sector, i.e., a selected word line as an erase operation voltage, and the drain and source terminal voltages of the memory cell are set to the ground voltage Vss of 0 V. A voltage difference occurs between the channel and the floating gate of the memory cell in the selected sector, and the electrons in the channel are injected into the floating gate by the Fowler-Nordheim tunnel phenomenon. An erase operation thus is made possible for increasing the threshold voltage of the memory cell.
With the flash memories of the above-mentioned types, a read error is caused when the threshold voltage of the memory cell assumes a negative value. It is therefore necessary to control the threshold voltage of the memory cell not to assume a negative value. For this purpose, the write operation sequence shown in FIG. 29 is executed in the prior art. In the write operation for the AND type constituting the third prior art described above, for example, a unit write time is set for a memory cell group (sector) connected to a predetermined word line in a memory cell array and data are written collectively, after which the data are read from the memory cells. If there is any memory cell in which data are not sufficiently written, a rewrite operation (verify operation) is performed. The word line potential at the time of the verify operation for checking whether the threshold voltage of a memory cell has reached a write threshold voltage or not is set to 1.5 V, for example, as a value at which the threshold voltage of none of the memory cells of the memory cell group in the sector assumes a negative voltage, taking the expansion of the distribution of the write threshold voltage into consideration.
xe2x80x9cSymposium on VLSI Technology Digest of Technical Papersxe2x80x9d pp.83-84, 1993, discloses an erratic imperfection, a phenomenon in which the electrons in the floating gate are injected or discharged through a tunnel film making up an insulation film, and therefore the internal electric field of the tunnel film is strengthened with the trap level in the tunnel film charged to a positive voltage with the result that the electrons are locally apt to be discharged from the floating gate, or a phenomenon in which the trap level is charged or not charged to a positive voltage depending on the number of rewrite operations. The above-mentioned conventional techniques cannot detect an erratic imperfection that occurs during the write operation as shown in FIG. 26 and thus poses the problem that upon occurrence of an erratic imperfection, accurate information cannot be read out from the semiconductor nonvolatile memory apparatus.
The write operation according to each of the above-mentioned types is for decreasing the threshold voltage of a selected memory cell. The AND-type apparatus, as described in the related papers, comprises a sense latch circuit for performing the operation of latching the write data for each bit line of a memory cell and performs the write operations for each sector collectively. A negative voltage of xe2x88x929 V is applied to the control gate, i.e., a word line of the memory cell, and the drain terminal voltage of the memory cell is set to 4 V for the selected cell and to 0 V for the non-selected cells according to the data of the sense latch circuit. A voltage difference occurs between the floating gate and the drain of the selected memory cell so that the electrons in the floating gate are drawn toward the drain by the Fowler-Nordheim tunnel phenomenon. In the non-selected memory cells, the voltage difference between the floating gate and the drain is so small that the electrons are prevented from being discharged from the floating gate.
In the write operation, on the other hand, the threshold voltage of the memory cells in the non-selected sectors slightly drops depending on the selected drain terminal voltage. In order to prevent this, a source voltage Vcc is applied to the non-selected word lines.
For the conventional semiconductor nonvolatile memory apparatus of AND type, the breakdown voltage of the MOS transistors making up the apparatus is required to be not less than 16 V providing a word line voltage not for the write operation but for the erase operation at which the potential difference is highest. In order to secure this breakdown voltage, the gate insulation film of each MOS transistor is increased to the thickness of not less than 25 nm, for example, to reduce the field strength applied to the gate oxide film while at the same time making a diffusion layer structure of a high breakdown voltage, and even when using a minimum rule of 0.4 xcexcm, the gate length is required to be 1.5 xcexcm or more, for example. As a result, the layout area of the MOS transistor is increased, thereby leading to the problem of an increased chip size of the semiconductor nonvolatile memory apparatus.
As such a flash memory, a flash memory of AND type is suggested in JP-A-7-176705, for example. FIG. 19 is a connection diagram of memory cells, and FIG. 20 is a schematic diagram showing a layout according to JP-A-7-176705 shown in FIG. 1. A plurality of memory cells are connected along the columns as a unit block. The drain of each memory cell is connected to a bit line through a MOS transistor, and the source of each memory cell is connected to a common source line through a MOS transistor. Also, the bit line is connected with a plurality of unit blocks. As shown in FIG. 20, a common source line is formed of a diffusion layer in the vertical direction between the bit lines as designated by L (SL), and further, is wired using a metal line M1 (SL) in the same layer as the bit lines in the direction parallel to a plurality of the bit lines.
With the conventional flash memory of AND type described above, the read operation and the verify operation for the threshold voltage of the memory cell after the rewrite operation are performed collectively for each sector of the memory cells connected to the word lines. In view of the fact that the common source line L (SL) is formed of a diffusion layer, a voltage effect occurs in the common source line L (SL) by the memory cell current flowing in the common source line L (SL) as shown in the equivalent circuit of a memory cell array of FIG. 53. Consequently, a substrate bias is effectively applied to the memory cells to change the threshold voltage thereof. The amount of change of the threshold voltage varies depending on the information pattern stored in each memory cell and the position of the memory cell. The subsource lines are formed also of a diffusion layer. Since a current of an amount corresponding to not more than a single memory cell flows, however, the variations in the threshold voltage of the memory cells of a sector are not caused.
FIG. 56 shows the threshold voltage dependency on the position of a memory cell on a bit line. The substrate bias has the greatest effect on a memory cell farther from the source line so that the threshold voltage of the memory cell is increased by the substrate bias. The substrate bias becomes maximum in the case where all the bits of the memory cell are write bits, i.e., in the case where the threshold voltage is so low that a cell current flows. The threshold voltage takes the lowest value, on the other hand, in the case where only one bit of the cell adjacent to the source line is a write cell. This threshold voltage difference xcex94Vth causes variations of the threshold voltage among the memory cells in the sector.
For reading the memory information, it is necessary to reduce the threshold voltage difference xcex94Vth and to stabilize the read operation. For this purpose, the common source line M1 (SL) shown in FIG. 20 is required for each 32 bit lines. This, however, poses the problem that the area of the memory array section increases by 3% or more.
In view of this, an object of the present invention is to provide an electrically-rewritable semiconductor nonvolatile memory apparatus and a computer system using such a memory apparatus, in which an operation sequence is newly set, the erratic phenomenon is suppressed in the apparatus and the rewrite resistance can be improved.
Another object of the invention is to provide an electrically-rewritable semiconductor nonvolatile memory apparatus and a computer system using such a memory apparatus, in which the maximum voltage for the erase operation of the electrically-rewritable nonvolatile memory apparatus is reduced to almost the same level as the maximum operating voltage for write operation thereby to reduce the chip size.
Still another object of the invention is to provide an electrically-rewritable semiconductor nonvolatile memory apparatus, in which the operation of reading information is stabilized for each sector, i.e., the variations in threshold voltage are reduced and further the apparatus area is also reduced.
Among the disclosures of the invention in this patent application, representative ones will be briefly described below.
Specifically, a semiconductor nonvolatile memory apparatus for solving the first problem according to the present invention is applied as a representative semiconductor nonvolatile memory apparatus as shown in FIG. 2, comprising transistors of which the threshold voltage can be electrically rewritten (erased and written), in which the write operation (the operation for reducing the threshold voltage) sequence includes an operation sequence for reducing the threshold voltage for memory cells collectively or selectively, verifying the threshold voltages for each memory cell group newly connected to the word lines and then increasing the threshold voltages of all the memory cells collectively in accordance with the threshold voltage for each memory cell.
As shown in the functional block diagram of FIG. 12, there is provided a semiconductor nonvolatile memory apparatus comprising what is called a sense latch circuit including a flip-flop for performing the sense operation and the operation of latching the write data and and the data for increasing the threshold voltage and a circuit for setting recursive data in the flip-flop automatically for each bit in accordance with the threshold voltage of the memory cell after verification, wherein a built-in source voltage circuit generates a voltage for restoring the threshold voltage for a memory cell and a word line voltage for verify operation.
Also, a computer system according to the present invention comprises at least a central processing unit and peripheral circuits thereof in addition to the above-mentioned semiconductor nonvolatile memory apparatus.
In the above-mentioned semiconductor nonvolatile memory apparatus and the computer system using such a nonvolatile memory apparatus, an operation means for automatically verifying the threshold voltages collectively for each memory cell group connected to the word lines and, after that, performing the operation of increasing the threshold voltages collectively in accordance with the threshold voltage for each memory within the apparatus is included the write operation (the operation for reducing the threshold voltage) sequence. In this way, the threshold voltages of the memory cells that have dropped due to the erratic phenomenon can be restored and the threshold voltage distribution can thus be reduced. Further, the threshold voltage affected by the bits depleted by the erratic phenomenon can be restored selectively and thus an erroneous read operation can be prevented by reading the verify word line voltage at the ground potential (Vss).
For example, the threshold voltage of a memory cell is set to 1.5 V after write operation, the discharge of electrons from the floating gate and the verify operation are repeated, and the threshold voltage of all the memory cells to be written is reduced to not more than 1.5 V. After that, the potential of the selected word line is verified (read) at the ground potential (Vss), and the memory cells of which the threshold voltage has been reduced to less than 0 V (depletion) by the erratic phenomenon are selected. The data read from each of them are used as those for the flip-flop of the sense latch circuit, the bit line voltage, i.e., the drain voltage is selectively reduced to the ground potential (Vss), and the potential of the selected word line for which the write operation has been performed is increased to as high as about 16 V. Then, electrons are injected into the floating gate taking advantage of the Fowler-Nordheim tunnel phenomenon over the entire surface of the channel, thereby restoring the threshold voltage of the memory cells selectively. In view of the fact that the data of the flip-flops of the sense latch circuits connected to the memory cells not depleted assume a source voltage, no sufficient difference in field strength occurs between the channel potential (source voltage) and the word line during the operation of increasing the threshold voltage. The threshold voltage of the memory cells thus can be held at 1.5 V after write operation.
Also, according to the present invention, the number of rewrite operations can be remarkably improved without imposing any limitation on the number of rewrite operations taking the erratic phenomenon into consideration.
Further, low voltages can be supplied from a single voltage source by utilizing the Fowler-Nordheim tunnel phenomenon in the operation of restoring the threshold voltage of the memory cells.
As a result, in a semiconductor nonvolatile memory apparatus capable of electric rewrite operation, the write operation sequence including the verify operation in combination with the operation for restoring the threshold value can suppress the erratic phenomenon and thus can improve the breakdown voltage for rewrite operation. Especially, in a computer system or the like using such a memory apparatus, the lower voltage can reduce the power consumption and can improve the reliability.
Also, in the erase operation of a semiconductor nonvolatile memory apparatus for solving the second problem, as compared with the prior art in which a positive high voltage is applied only to a selected word line, the voltage for erase operation is distributed between a positive voltage applied to the word line and a negative voltage applied to the memory well according to the present invention. By the way, the absolute value of the memory well voltage is set to be about equal to or higher than the word line voltage for read operation.
FIG. 33 is a schematic diagram showing a memory mat according to the present invention. The sectors making up the memory mat of a semiconductor nonvolatile memory apparatus include a sector (selected sector) for which the erase operation is selected and a positive voltage is applied to the word line, a sector (non-selected sector) for which the erase operation is not selected and the word line voltage is different from the memory well voltage, and a sector (completely (non-selected sector) for which the erase operation is not selected and the word line voltage is equal to the source-drain voltage (channel voltage) of the memory cells.
The completely non-selected sector includes a memory cell in which a negative voltage is applied to the memory well and the channel voltage and the word line voltage assume the ground voltage in erase operation or a memory cell in which the memory well voltage, the channel voltage and the word line voltage all assume the ground voltage. In this case, the memory cells are connected in such a manner that each unit block includes a plurality of parallel-connected memory cells each with the drain thereof connected to the bit line through a MOS transistor and with the source thereof connected to the source line through a MOS transistor. Therefore, the selected sector and the non-selected sector exist in the same unit block, and the sectors making up the other blocks are completely non-selected sectors.
FIG. 35 is a model sectional view of a memory cell of a semiconductor nonvolatile memory apparatus. In order to apply a negative voltage to the memory cell, the DP well of the memory cell, the well of the above-mentioned MOS transistors and the well of a MOS transistor for transferring the potential of the source line and the bit line of the memory cell are formed within the blocking-isolation niso region in order to isolate them from the substrate p-sub of the memory apparatus.
A semiconductor nonvolatile memory apparatus according to the present invention, as shown in the functional block diagram of FIG. 37 thereof, comprises a circuit MWVC for segmenting the memory mat and switching the well voltage of the memory mat without disturbing the sector units, a row decoder circuit XDCR for selecting a word line, i.e., a sector, a sense latch circuit SL for performing the sense operation and the operation of latching the written data, and further a built-in power circuit VS for generating a word line voltage Vh constituting an erase operation voltage, a memory well voltage Vmw, a word line voltage V1 constituting a write operation voltage, a bit line voltage V1b, etc.
Also, the rise waveform of the erase voltage for the erase operation rises within several microseconds to several tens of microseconds with a load capacitance and thus prevents a sudden field strength from being applied to the memory cell. The semiconductor nonvolatile memory apparatus further comprises a mode control circuit MC for setting a timing in such a manner that the time when the memory well voltage rises to a predetermined voltage level is equal to the time when the word line voltage reaches a predetermined voltage level.
A computer system according to the present invention comprises, in addition to the above-mentioned semiconductor nonvolatile memory apparatus, at least a central processing unit and peripheral circuits thereof.
According to this invention, 12 V is applied to a selected word line through the row decoder circuit XDCR and xe2x88x924 V is applied to the memory well through the memory mat well switching circuit MWVC, thereby achieving the voltage 16 V applied to the memory cell considered necessary for the erase operation. As a result, the maximum voltage impressed on the MOS transistor of the row decoder circuit XDCR assumes 12 V. The breakdown voltage can thus be reduced from 16 V to 12 V.
In the write operation, on the other hand, xe2x88x929 V is applied to the word line of the selected memory cell through the row decoder circuit XDCR and 4 V is applied to the selected bit line according to the data of the sense latch circuit SL thereby to set the non-selected word line to the source voltage Vcc. For this reason, the MOS transistor of the row decoder circuit XDCR is required to select xe2x88x929 V and the source voltage Vcc, and the breakdown voltage of the MOS transistor is required to be 12.3 V with respect to the source voltage Vcc of 3.3 V.
In a MOS transistor making up the apparatus according to the present invention, therefore, a maximum breakdown voltage of 12.3 V is secured by the erase operation and the write operation described above, and thus the gate length that can be used is about 1 xcexcm.
Also, the memory well voltage of only the non-selected sectors contained in the same block as the selector block is disturbed in a system, in which each unit block includes a plurality of parallel memory cells with a common drain thereof connected to the bit line through a MOS transistor and the source of the particular unit block connected to the source line through a MOS transistor. As a result, the disturb life time can be reduced from 8 k bits (1 k=1024 bits) which is the number of sectors intersecting the bit line to 64 bits which is the number of sectors constituting a unit block, i.e., to {fraction (1/128)}, thus making it possible to improve the reliability.
FIG. 49 shows a metal wiring layer layout with a plurality of unit blocks arranged along the bit lines for solving the third problem, and FIG. 2 is a model diagram showing a metal wiring layer layout of a memory mat.
The memory mat in a memory cell array for a semiconductor nonvolatile memory apparatus according to the present invention is so configured in layout that a common source line (M1) is arranged in parallel to the word lines but not between the bit lines. The metal wiring layer of the common source line (M1) is formed in the fabrication step before the metal wiring layer used for the bit lines. A common source line (M2 or more) arranged along the columns (parallel to the bit lines) in the same metal wiring layer as the bit lines is configured in a layout at the end of the memory mat including a dummy memory cell column. Also, the width of the common source line is larger than the width of the bit line by a factor of about 100.
In a method of connecting the memory cells according to this invention, unit blocks each including a plurality of memory cells connected to the bit lines through a MOS transistor have the respective sources thereof connected to the common source line (M1).
In a semiconductor nonvolatile memory apparatus according to the present invention with memory mats segmented without affecting the sector units, as shown in the functional block diagram of FIG. 57, comprises a row decoder circuit XDCR for selecting a word line, i.e., a sector, a sense latch circuit SNS for performing the sense operation and the operation of latching the data written, and further a built-in power circuit VS for generating a rewrite operation voltage.
The common source line of the memory cell array mat is connected for each memory cell column of the unit blocks, and no dummy memory cell column is arranged between the bit lines, thereby reducing the size of the memory mat.
Also, in view of the fact that the width of the common source wiring is larger than that of the bit line by a factor of about 100, the substrate bias imposed on the memory cells connected the same word line, i.e., the same sector is constant, and therefore the variations in the threshold voltage decrease. Consequently, the operation of reading information is stabilized for each sector.